1. Field of the Invention
The present invention relates generally to the field of memory management and, more specifically, to a cache auto-clean algorithm and supporting hardware design.
2. Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as “L2 cache”). The L2 cache is a large on-chip memory that serves as an intermediate point between an external memory (e.g., frame buffer memory) and internal clients of the memory subsystem (referred to herein as the “clients”). The L2 cache temporarily stores data that the clients are reading from and writing to the external memory (referred to herein as “DRAM”).
During a write operation, where a client transmits data that needs to be committed to a DRAM, the data to be written is first transmitted to the L2 cache and is held there until an opportune time to push the data to the DRAM arises. Data present in the data cache is considered “dirty” until the data is written to the DRAM, after which the memory space in the data cache can be cleaned and made available for other data. For systems requiring high data throughput, like graphics systems, writing the dirty data to memory as efficiently as possible is critical to overall system performance. Doing so creates free memory space in the L2 cache for new read/write operations.
As is well known, each block of dirty data in the L2 cache has an associated location within a specific bank page of the DRAM, where the dirty data is written. To optimize memory accesses by mitigating delays resulting from the waiting for DRAM bank pages to pre-charge, the number of write operations from the L2 cache to a particular DRAM bank page at any given time should be maximized.
As the foregoing illustrates, what is needed in the art is a technique to efficiently write dirty data from the L2 cache to the DRAM.